* Dominic.Rath@gmx.de *
* Copyright (C) 2009 Michael Schwingen *
* michael@schwingen.org *
+ * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
+ * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
#include "imp.h"
#include "cfi.h"
#include "non_cfi.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
/* CFI fixups foward declarations */
static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
-static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
+static void cfi_fixup_reversed_erase_regions(struct flash_bank *flash, void *param);
/* fixup after reading cmdset 0002 primary query table */
static const struct cfi_fixup cfi_0002_fixups[] = {
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
- {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
+ {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
+ {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
+ {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
+ {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
}
return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
}
-
}
static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
}
}
+static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
+{
+ uint8_t command[CFI_MAX_BUS_WIDTH];
+
+ cfi_command(bank, cmd, command);
+ return target_write_memory(bank->target, address, bank->bus_width, 1, command);
+}
+
/* read unsigned 8-bit value from the bank
* flash banks are expected to be made of similar chips
* the query result should be the same for all
*/
-static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
+static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
{
struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
- target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ int retval;
+ retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ if (retval != ERROR_OK)
+ return retval;
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
- return data[0];
+ *val = data[0];
else
- return data[bank->bus_width - 1];
+ *val = data[bank->bus_width - 1];
+
+ return ERROR_OK;
}
/* read unsigned 8-bit value from the bank
* in case of a bank made of multiple chips,
* the individual values are ORed
*/
-static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
+static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
{
struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
int i;
- target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ int retval;
+ retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ if (retval != ERROR_OK)
+ return retval;
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
{
for (i = 0; i < bank->bus_width / bank->chip_width; i++)
data[0] |= data[i];
- return data[0];
+ *val = data[0];
}
else
{
for (i = 0; i < bank->bus_width / bank->chip_width; i++)
value |= data[bank->bus_width - 1 - i];
- return value;
+ *val = value;
}
+ return ERROR_OK;
}
-static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
+static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
{
struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 2];
+ int retval;
if (cfi_info->x16_as_x8)
{
uint8_t i;
for (i = 0;i < 2;i++)
- target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
+ {
+ retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
&data[i*bank->bus_width]);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ } else
+ {
+ retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
+ if (retval != ERROR_OK)
+ return retval;
}
- else
- target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
- return data[0] | data[bank->bus_width] << 8;
+ *val = data[0] | data[bank->bus_width] << 8;
else
- return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
+ *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
+
+ return ERROR_OK;
}
-static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
+static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
{
struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 4];
+ int retval;
if (cfi_info->x16_as_x8)
{
uint8_t i;
for (i = 0;i < 4;i++)
- target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
+ {
+ retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
&data[i*bank->bus_width]);
+ if (retval != ERROR_OK)
+ return retval;
+ }
}
else
- target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
+ {
+ retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
+ if (retval != ERROR_OK)
+ return retval;
+ }
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
- return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
+ *val = data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
else
- return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
+ *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
+
+ return ERROR_OK;
+}
+
+static int cfi_reset(struct flash_bank *bank)
+{
+ struct cfi_flash_bank *cfi_info = bank->driver_priv;
+ int retval = ERROR_OK;
+
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (cfi_info->manufacturer == 0x20 &&
+ (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
+ {
+ /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
+ * so we send an extra 0xF0 reset to fix the bug */
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+
+ return retval;
}
static void cfi_intel_clear_status_register(struct flash_bank *bank)
{
struct target *target = bank->target;
- uint8_t command[8];
if (target->state != TARGET_HALTED)
{
exit(-1);
}
- cfi_command(bank, 0x50, command);
- target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
}
-uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
+static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
{
uint8_t status;
- while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
+ int retval = ERROR_OK;
+
+ for (;;)
{
- LOG_DEBUG("status: 0x%x", status);
+ if (timeout-- < 0)
+ {
+ LOG_ERROR("timeout while waiting for WSM to become ready");
+ return ERROR_FAIL;
+ }
+
+ retval = cfi_get_u8(bank, 0, 0x0, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (status & 0x80)
+ break;
+
alive_sleep(1);
}
LOG_DEBUG("status: 0x%x", status);
- if ((status & 0x80) != 0x80)
- {
- LOG_ERROR("timeout while waiting for WSM to become ready");
- }
- else if (status != 0x80)
+ if (status != 0x80)
{
LOG_ERROR("status register: 0x%x", status);
if (status & 0x2)
LOG_ERROR("Block Erase Suspended");
cfi_intel_clear_status_register(bank);
+
+ retval = ERROR_FAIL;
}
- return status;
+ *val = status;
+ return retval;
}
-int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
+static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
{
uint8_t status, oldstatus;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
+ int retval;
- oldstatus = cfi_get_u8(bank, 0, 0x0);
+ retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
+ if (retval != ERROR_OK)
+ return retval;
do {
- status = cfi_get_u8(bank, 0, 0x0);
+ retval = cfi_get_u8(bank, 0, 0x0, &status);
+
+ if (retval != ERROR_OK)
+ return retval;
+
if ((status ^ oldstatus) & 0x40) {
if (status & cfi_info->status_poll_mask & 0x20) {
- oldstatus = cfi_get_u8(bank, 0, 0x0);
- status = cfi_get_u8(bank, 0, 0x0);
+ retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_get_u8(bank, 0, 0x0, &status);
+ if (retval != ERROR_OK)
+ return retval;
if ((status ^ oldstatus) & 0x40) {
LOG_ERROR("dq5 timeout, status: 0x%x", status);
return(ERROR_FLASH_OPERATION_FAILED);
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
- struct target *target = bank->target;
- uint8_t command[8];
+ struct cfi_intel_pri_ext *pri_ext;
+
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+ pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_info->pri_ext = pri_ext;
- pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
- pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
- pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
+ if (retval != ERROR_OK)
+ return retval;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_reset(bank)) != ERROR_OK)
{
return retval;
}
return ERROR_FLASH_BANK_INVALID;
}
- pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
- pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
- pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
- pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
- pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
+ retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);
- pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
- pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
+ if (retval != ERROR_OK)
+ return retval;
- LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
+ LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
- pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
+ if (retval != ERROR_OK)
+ return retval;
if (pri_ext->num_protection_fields != 1)
{
LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
}
- pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
- pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
- pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
+ retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
- struct target *target = bank->target;
- uint8_t command[8];
+ struct cfi_spansion_pri_ext *pri_ext;
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+
+ pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_info->pri_ext = pri_ext;
- pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
- pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
- pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
+ if (retval != ERROR_OK)
+ return retval;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
return ERROR_FLASH_BANK_INVALID;
}
- pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
- pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
- pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
- pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
- pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
- pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
- pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
- pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
- pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
- pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
- pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
- pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
- pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
pri_ext->EraseSuspend, pri_ext->BlkProt);
LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
- LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
+ LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
int retval;
struct cfi_atmel_pri_ext atmel_pri_ext;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
- struct target *target = bank->target;
- uint8_t command[8];
+ struct cfi_spansion_pri_ext *pri_ext;
+
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+
+ pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
* but a different primary extended query table.
cfi_info->pri_ext = pri_ext;
- atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
- atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
- atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
+ if (retval != ERROR_OK)
+ return retval;
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
pri_ext->pri[1] = atmel_pri_ext.pri[1];
pri_ext->pri[2] = atmel_pri_ext.pri[2];
- atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
- atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
pri_ext->major_version = atmel_pri_ext.major_version;
pri_ext->minor_version = atmel_pri_ext.minor_version;
- atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
- atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
- atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
- atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
+ printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
+ printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
buf += printed;
return ERROR_FLASH_BANK_INVALID;
}
- uint16_t chip_width, bus_width;
- COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], bus_width);
- COMMAND_PARSE_NUMBER(u16, CMD_ARGV[4], chip_width);
-
- if ((chip_width > CFI_MAX_CHIP_WIDTH)
- || (bus_width > CFI_MAX_BUS_WIDTH))
+ /* both widths must:
+ * - not exceed max value;
+ * - not be null;
+ * - be equal to a power of 2.
+ * bus must be wide enought to hold one chip */
+ if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
+ || (bank->bus_width > CFI_MAX_BUS_WIDTH)
+ || (bank->chip_width == 0)
+ || (bank->bus_width == 0)
+ || (bank->chip_width & (bank->chip_width - 1))
+ || (bank->bus_width & (bank->bus_width - 1))
+ || (bank->chip_width > bank->bus_width))
{
LOG_ERROR("chip and bus width have to specified in bytes");
return ERROR_FLASH_BANK_INVALID;
cfi_info = malloc(sizeof(struct cfi_flash_bank));
cfi_info->probed = 0;
+ cfi_info->erase_region_info = NULL;
+ cfi_info->pri_ext = NULL;
bank->driver_priv = cfi_info;
cfi_info->write_algorithm = NULL;
cfi_info->write_algorithm = NULL;
/* bank wasn't probed yet */
- cfi_info->qry[0] = -1;
+ cfi_info->qry[0] = 0xff;
return ERROR_OK;
}
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct target *target = bank->target;
- uint8_t command[8];
int i;
cfi_intel_clear_status_register(bank);
for (i = first; i <= last; i++)
{
- cfi_command(bank, 0x20, command);
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0xd0, command);
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
- if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ), &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (status == 0x80)
bank->sectors[i].is_erased = 1;
else
{
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
}
}
- cfi_command(bank, 0xff, command);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
-
+ return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
}
static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- struct target *target = bank->target;
- uint8_t command[8];
int i;
for (i = first; i <= last; i++)
{
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x80, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x30, command);
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
bank->sectors[i].is_erased = 1;
else
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
}
}
- cfi_command(bank, 0xf0, command);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
}
static int cfi_erase(struct flash_bank *bank, int first, int last)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
- struct target *target = bank->target;
- uint8_t command[8];
int retry = 0;
int i;
* instant individual block locking (bit 5).
*/
if (!(pri_ext->feature_support & 0x28))
+ {
+ LOG_ERROR("lock/unlock not supported on flash");
return ERROR_FLASH_OPERATION_FAILED;
+ }
cfi_intel_clear_status_register(bank);
for (i = first; i <= last; i++)
{
- cfi_command(bank, 0x60, command);
- LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
if (set)
{
- cfi_command(bank, 0x01, command);
- LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
}
else
{
- cfi_command(bank, 0xd0, command);
- LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
if (!(pri_ext->feature_support & 0x20))
{
/* Clear lock bits operation may take up to 1.4s */
- cfi_intel_wait_status_busy(bank, 1400);
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 1400, &status);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
uint8_t block_status;
/* read block lock bit, to verify status */
- cfi_command(bank, 0x90, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
{
return retval;
}
- block_status = cfi_get_u8(bank, i, 0x2);
+ retval = cfi_get_u8(bank, i, 0x2, &block_status);
+ if (retval != ERROR_OK)
+ return retval;
if ((block_status & 0x1) != set)
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
- cfi_command(bank, 0x70, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
{
return retval;
}
- cfi_intel_wait_status_busy(bank, 10);
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 10, &status);
+ if (retval != ERROR_OK)
+ return retval;
if (retry > 10)
return ERROR_FLASH_OPERATION_FAILED;
*/
if ((!set) && (!(pri_ext->feature_support & 0x20)))
{
+ /* FIX!!! this code path is broken!!!
+ *
+ * The correct approach is:
+ *
+ * 1. read out current protection status
+ *
+ * 2. override read out protection status w/unprotected.
+ *
+ * 3. re-protect what should be protected.
+ *
+ */
for (i = 0; i < bank->num_sectors; i++)
{
if (bank->sectors[i].is_protected == 1)
{
cfi_intel_clear_status_register(bank);
- cfi_command(bank, 0x60, command);
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x01, command);
- if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
{
return retval;
}
- cfi_intel_wait_status_busy(bank, 100);
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 100, &status);
+ if (retval != ERROR_OK)
+ return retval;
}
}
}
- cfi_command(bank, 0xff, command);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
}
static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
{
+ LOG_ERROR("Invalid sector range");
return ERROR_FLASH_SECTOR_INVALID;
}
{
case 1:
case 3:
- cfi_intel_protect(bank, set, first, last);
+ return cfi_intel_protect(bank, set, first, last);
break;
default:
LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
- break;
- }
-
- return ERROR_OK;
-}
-
-/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
-static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
-{
- /* struct target *target = bank->target; */
-
- int i;
-
- /* NOTE:
- * The data to flash must not be changed in endian! We write a bytestrem in
- * target byte order already. Only the control and status byte lane of the flash
- * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
- * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
- */
-
-#if 0
- if (target->endianness == TARGET_LITTLE_ENDIAN)
- {
-#endif
- /* shift bytes */
- for (i = 0; i < bank->bus_width - 1; i++)
- word[i] = word[i + 1];
- word[bank->bus_width - 1] = byte;
-#if 0
+ return ERROR_FAIL;
}
- else
- {
- /* shift bytes */
- for (i = bank->bus_width - 1; i > 0; i--)
- word[i] = word[i - 1];
- word[0] = byte;
- }
-#endif
}
/* Convert code image to target endian */
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
struct reg_param reg_params[7];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t write_command_val, busy_pattern_val, error_pattern_val;
/* Get a workspace buffer for the data to flash starting with 32k size.
Half size until buffer would be smaller 256 Bytem then fail back */
/* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
{
buffer_size /= 2;
if (buffer_size <= 256)
busy_pattern_val = cfi_command_val(bank, 0x80);
error_pattern_val = cfi_command_val(bank, 0x7e);
- LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
+ LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
/* Programming main loop */
while (count > 0)
buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
- LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
+ LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
/* Execute algorithm, assume breakpoint for last instruction */
retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
if (wsm_error)
{
/* read status register (outputs debug inforation) */
- cfi_intel_wait_status_busy(bank, 100);
+ uint8_t status;
+ cfi_intel_wait_status_busy(bank, 100, &status);
cfi_intel_clear_status_register(bank);
retval = ERROR_FLASH_OPERATION_FAILED;
goto cleanup;
buffer += thisrun_count;
address += thisrun_count;
count -= thisrun_count;
+
+ keep_alive();
}
/* free up resources */
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
struct target *target = bank->target;
struct reg_param reg_params[10];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t status;
- int retval, retvaltemp;
- int exit_code = ERROR_OK;
+ int retval = ERROR_OK;
/* input parameters - */
/* R0 = source address */
/* convert bus-width dependent algorithm code to correct endiannes */
target_code = malloc(target_code_size);
+ if (target_code == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
/* allocate working area */
}
/* the following code still assumes target code is fixed 24*4 bytes */
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
{
buffer_size /= 2;
if (buffer_size <= 256)
{
uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
- retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
+ retval = target_write_buffer(target, source->address, thisrun_count, buffer);
+ if (retval != ERROR_OK)
+ {
+ break;
+ }
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
cfi_info->write_algorithm->address,
cfi_info->write_algorithm->address + ((target_code_size) - 4),
10000, &armv4_5_info);
+ if (retval != ERROR_OK)
+ {
+ break;
+ }
status = buf_get_u32(reg_params[5].value, 0, 32);
-
- if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
+ if (status != 0x80)
{
- LOG_DEBUG("status: 0x%" PRIx32 , status);
- exit_code = ERROR_FLASH_OPERATION_FAILED;
+ LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
destroy_reg_param(®_params[8]);
destroy_reg_param(®_params[9]);
- return exit_code;
+ return retval;
}
static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- uint8_t command[8];
cfi_intel_clear_status_register(bank);
- cfi_command(bank, 0x40, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
{
return retval;
}
return retval;
}
- if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max), &status);
+ if (retval != 0x80)
{
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- uint8_t command[8];
/* Calculate buffer size and boundary mask */
+ /* buffersize is (buffer size per chip) * (number of chips) */
+ /* bufferwsize is buffersize in words */
uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
uint32_t buffermask = buffersize-1;
- uint32_t bufferwsize;
+ uint32_t bufferwsize = buffersize / bank->bus_width;
/* Check for valid range */
if (address & buffermask)
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
- switch (bank->chip_width)
- {
- case 4 : bufferwsize = buffersize / 4; break;
- case 2 : bufferwsize = buffersize / 2; break;
- case 1 : bufferwsize = buffersize; break;
- default:
- LOG_ERROR("Unsupported chip width %d", bank->chip_width);
- return ERROR_FLASH_OPERATION_FAILED;
- }
-
- bufferwsize/=(bank->bus_width / bank->chip_width);
-
/* Check for valid size */
if (wordcount > bufferwsize)
cfi_intel_clear_status_register(bank);
/* Initiate buffer operation _*/
- cfi_command(bank, 0xE8, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
{
return retval;
}
- if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
+ uint8_t status;
+ retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
+ if (retval != ERROR_OK)
+ return retval;
+ if (status != 0x80)
{
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
}
/* Write buffer wordcount-1 and data words */
- cfi_command(bank, bufferwsize-1, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
{
return retval;
}
}
/* Commit write operation */
- cfi_command(bank, 0xd0, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
{
return retval;
}
- if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
+
+ retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (status != 0x80)
{
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
struct target *target = bank->target;
- uint8_t command[8];
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0xa0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- uint8_t command[8];
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
/* Calculate buffer size and boundary mask */
+ /* buffersize is (buffer size per chip) * (number of chips) */
+ /* bufferwsize is buffersize in words */
uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
uint32_t buffermask = buffersize-1;
- uint32_t bufferwsize;
+ uint32_t bufferwsize = buffersize / bank->bus_width;
/* Check for valid range */
if (address & buffermask)
LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
- switch (bank->chip_width)
- {
- case 4 : bufferwsize = buffersize / 4; break;
- case 2 : bufferwsize = buffersize / 2; break;
- case 1 : bufferwsize = buffersize; break;
- default:
- LOG_ERROR("Unsupported chip width %d", bank->chip_width);
- return ERROR_FLASH_OPERATION_FAILED;
- }
-
- bufferwsize/=(bank->bus_width / bank->chip_width);
/* Check for valid size */
if (wordcount > bufferwsize)
}
// Unlock
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
{
return retval;
}
// Buffer load command
- cfi_command(bank, 0x25, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
{
return retval;
}
/* Write buffer wordcount-1 and data words */
- cfi_command(bank, bufferwsize-1, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
{
return retval;
}
}
/* Commit write operation */
- cfi_command(bank, 0x29, command);
- if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
{
return retval;
}
return ERROR_FLASH_OPERATION_FAILED;
}
-int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct cfi_flash_bank *cfi_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t address = bank->base + offset;
+ uint32_t read_p;
+ int align; /* number of unaligned bytes */
+ uint8_t current_word[CFI_MAX_BUS_WIDTH];
+ int i;
+ int retval;
+
+ LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
+ (int)count, (unsigned)offset);
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset + count > bank->size)
+ return ERROR_FLASH_DST_OUT_OF_BANK;
+
+ if (cfi_info->qry[0] != 'Q')
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ /* start at the first byte of the first word (bus_width size) */
+ read_p = address & ~(bank->bus_width - 1);
+ if ((align = address - read_p) != 0)
+ {
+ LOG_INFO("Fixup %d unaligned read head bytes", align);
+
+ /* read a complete word from flash */
+ if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
+ return retval;
+
+ /* take only bytes we need */
+ for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
+ *buffer++ = current_word[i];
+
+ read_p += bank->bus_width;
+ }
+
+ align = count / bank->bus_width;
+ if (align)
+ {
+ if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
+ return retval;
+
+ read_p += align * bank->bus_width;
+ buffer += align * bank->bus_width;
+ count -= align * bank->bus_width;
+ }
+
+ if (count)
+ {
+ LOG_INFO("Fixup %d unaligned read tail bytes", count);
+
+ /* read a complete word from flash */
+ if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
+ return retval;
+
+ /* take only bytes we need */
+ for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
+ *buffer++ = current_word[i];
+ }
+
+ return ERROR_OK;
+}
+
+static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t address = bank->base + offset; /* address of first byte to be programmed */
- uint32_t write_p, copy_p;
+ uint32_t write_p;
int align; /* number of unaligned bytes */
int blk_count; /* number of bus_width bytes for block copy */
uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
{
LOG_INFO("Fixup %d unaligned head bytes", align);
- for (i = 0; i < bank->bus_width; i++)
- current_word[i] = 0;
- copy_p = write_p;
-
- /* copy bytes before the first write address */
- for (i = 0; i < align; ++i, ++copy_p)
- {
- uint8_t byte;
- if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
- {
- return retval;
- }
- cfi_add_byte(bank, current_word, byte);
- }
-
- /* add bytes from the buffer */
- for (; (i < bank->bus_width) && (count > 0); i++)
- {
- cfi_add_byte(bank, current_word, *buffer++);
- count--;
- copy_p++;
- }
+ /* read a complete word from flash */
+ if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
+ return retval;
- /* if the buffer is already finished, copy bytes after the last write address */
- for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
- {
- uint8_t byte;
- if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
- {
- return retval;
- }
- cfi_add_byte(bank, current_word, byte);
- }
+ /* replace only bytes that must be written */
+ for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
+ current_word[i] = *buffer++;
retval = cfi_write_word(bank, current_word, write_p);
if (retval != ERROR_OK)
return retval;
- write_p = copy_p;
+ write_p += bank->bus_width;
}
/* handle blocks of bus_size aligned bytes */
{
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
- //adjust buffersize for chip width
+ /* Calculate buffer size and boundary mask */
+ /* buffersize is (buffer size per chip) * (number of chips) */
+ /* bufferwsize is buffersize in words */
uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
uint32_t buffermask = buffersize-1;
- uint32_t bufferwsize;
-
- switch (bank->chip_width)
- {
- case 4 : bufferwsize = buffersize / 4; break;
- case 2 : bufferwsize = buffersize / 2; break;
- case 1 : bufferwsize = buffersize; break;
- default:
- LOG_ERROR("Unsupported chip width %d", bank->chip_width);
- return ERROR_FLASH_OPERATION_FAILED;
- }
-
- bufferwsize/=(bank->bus_width / bank->chip_width);
+ uint32_t bufferwsize = buffersize / bank->bus_width;
/* fall back to memory writes */
while (count >= (uint32_t)bank->bus_width)
if (fallback)
{
for (i = 0; i < bank->bus_width; i++)
- current_word[i] = 0;
-
- for (i = 0; i < bank->bus_width; i++)
- {
- cfi_add_byte(bank, current_word, *buffer++);
- }
+ current_word[i] = *buffer++;
retval = cfi_write_word(bank, current_word, write_p);
if (retval != ERROR_OK)
}
/* return to read array mode, so we can read from flash again for padding */
- cfi_command(bank, 0xf0, current_word);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, current_word);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if ((retval = cfi_reset(bank)) != ERROR_OK)
{
return retval;
}
{
LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
- copy_p = write_p;
- for (i = 0; i < bank->bus_width; i++)
- current_word[i] = 0;
+ /* read a complete word from flash */
+ if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
+ return retval;
+
+ /* replace only bytes that must be written */
+ for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
+ current_word[i] = *buffer++;
- for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
- {
- cfi_add_byte(bank, current_word, *buffer++);
- count--;
- }
- for (; i < bank->bus_width; ++i, ++copy_p)
- {
- uint8_t byte;
- if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
- {
- return retval;
- }
- cfi_add_byte(bank, current_word, byte);
- }
retval = cfi_write_word(bank, current_word, write_p);
if (retval != ERROR_OK)
return retval;
}
/* return to read array mode */
- cfi_command(bank, 0xf0, current_word);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, current_word);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ return cfi_reset(bank);
}
-static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
+static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
{
(void) param;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
static int cfi_query_string(struct flash_bank *bank, int address)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct target *target = bank->target;
int retval;
- uint8_t command[8];
- cfi_command(bank, 0x98, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
{
return retval;
}
- cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
- cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
- cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
+ retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_reset(bank)) != ERROR_OK)
{
return retval;
}
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- uint8_t command[8];
int num_sectors = 0;
int i;
int sector = 0;
uint32_t unlock1 = 0x555;
uint32_t unlock2 = 0x2aa;
int retval;
+ uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
if (bank->target->state != TARGET_HALTED)
{
}
cfi_info->probed = 0;
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+ if(cfi_info->erase_region_info)
+ {
+ free(cfi_info->erase_region_info);
+ cfi_info->erase_region_info = NULL;
+ }
/* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
* while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
}
/* switch to read identifier codes mode ("AUTOSELECT") */
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x90, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
{
return retval;
}
- if (bank->chip_width == 1)
+ if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
{
- uint8_t manufacturer, device_id;
- if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
- {
- return retval;
- }
- if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
- {
- return retval;
- }
- cfi_info->manufacturer = manufacturer;
- cfi_info->device_id = device_id;
+ return retval;
}
- else if (bank->chip_width == 2)
+ if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
{
- if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
- {
- return retval;
- }
- if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
- {
- return retval;
- }
+ return retval;
+ }
+ switch (bank->chip_width) {
+ case 1:
+ cfi_info->manufacturer = *value_buf0;
+ cfi_info->device_id = *value_buf1;
+ break;
+ case 2:
+ cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
+ cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
+ break;
+ case 4:
+ cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
+ cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
+ break;
+ default:
+ LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
+ return ERROR_FLASH_OPERATION_FAILED;
}
LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
/* switch back to read array mode */
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_reset(bank)) != ERROR_OK)
{
return retval;
}
*/
if (cfi_info->not_cfi == 0)
{
- int retval;
-
/* enter CFI query mode
* according to JEDEC Standard No. 68.01,
* a single bus sequence with address = 0x55, data = 0x98 should put
if (retval != ERROR_OK)
return retval;
- cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
- cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
- cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
- cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
+ retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
- cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
- cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
- cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
- cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
- cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
- cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
- cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
- cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
- cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
- cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
- cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
- cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
-
- LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
+ retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
+ if (retval != ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
- cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
- cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
- cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
- cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
+ uint8_t data;
+ retval = cfi_query_u8(bank, 0, 0x27, &data);
+ if (retval != ERROR_OK)
+ return retval;
+ cfi_info->dev_size = 1 << data;
+
+ retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
if (cfi_info->num_erase_regions)
{
- cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
+ cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
+ * cfi_info->num_erase_regions);
for (i = 0; i < cfi_info->num_erase_regions; i++)
{
- cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
+ retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
/* return to read array mode
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
- cfi_command(bank, 0xf0, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
- {
- return retval;
- }
- cfi_command(bank, 0xff, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_reset(bank)) != ERROR_OK)
{
return retval;
}
return cfi_probe(bank);
}
-
static int cfi_intel_protect_check(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
- struct target *target = bank->target;
- uint8_t command[CFI_MAX_BUS_WIDTH];
int i;
/* check if block lock bits are supported on this device */
if (!(pri_ext->blk_status_reg_mask & 0x1))
return ERROR_FLASH_OPERATION_FAILED;
- cfi_command(bank, 0x90, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
{
return retval;
}
for (i = 0; i < bank->num_sectors; i++)
{
- uint8_t block_status = cfi_get_u8(bank, i, 0x2);
+ uint8_t block_status;
+ retval = cfi_get_u8(bank, i, 0x2, &block_status);
+ if (retval != ERROR_OK)
+ return retval;
if (block_status & 1)
bank->sectors[i].is_protected = 1;
bank->sectors[i].is_protected = 0;
}
- cfi_command(bank, 0xff, command);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
}
static int cfi_spansion_protect_check(struct flash_bank *bank)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- struct target *target = bank->target;
- uint8_t command[8];
int i;
- cfi_command(bank, 0xaa, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x55, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
{
return retval;
}
- cfi_command(bank, 0x90, command);
- if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
{
return retval;
}
for (i = 0; i < bank->num_sectors; i++)
{
- uint8_t block_status = cfi_get_u8(bank, i, 0x2);
+ uint8_t block_status;
+ retval = cfi_get_u8(bank, i, 0x2, &block_status);
+ if (retval != ERROR_OK)
+ return retval;
if (block_status & 1)
bank->sectors[i].is_protected = 1;
bank->sectors[i].is_protected = 0;
}
- cfi_command(bank, 0xf0, command);
- return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
}
static int cfi_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
{
int printed;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- if (cfi_info->qry[0] == (char)-1)
+ if (cfi_info->qry[0] == 0xff)
{
printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
return ERROR_OK;
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
+ printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
}
struct flash_driver cfi_flash = {
- .name = "cfi",
- .flash_bank_command = &cfi_flash_bank_command,
- .erase = &cfi_erase,
- .protect = &cfi_protect,
- .write = &cfi_write,
- .probe = &cfi_probe,
- .auto_probe = &cfi_auto_probe,
- .erase_check = &default_flash_blank_check,
- .protect_check = &cfi_protect_check,
- .info = &cfi_info,
- };
+ .name = "cfi",
+ .flash_bank_command = cfi_flash_bank_command,
+ .erase = cfi_erase,
+ .protect = cfi_protect,
+ .write = cfi_write,
+ .read = cfi_read,
+ .probe = cfi_probe,
+ .auto_probe = cfi_auto_probe,
+ /* FIXME: access flash at bus_width size */
+ .erase_check = default_flash_blank_check,
+ .protect_check = cfi_protect_check,
+ .info = get_cfi_info,
+};
projects / openocd-genbsdl / blobdiff